1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and more particularly, to a method of manufacturing a self-aligned contact (SAC) hole, which method facilitates providing a sufficient overlay margin in a photolithography process.
2. Description of the Related Art
As the miniaturization of semiconductor devices progresses, the processes to achieve the required implementation are becoming increasingly difficult and challenging. For example, in a photolithographic process used for forming miniature patterns, as an overlay margin becomes smaller, a small contact process becomes more difficult to perform.
As an alternative to securing an overlay margin, SAC etching processes have been employed. The SAC etching process takes advantage of an etching selectivity between two different kinds of insulating layers to form a contact hole. SAC etching has an advantage in that a sufficient overlay margin can be provided during photolithography. However, as integration of semiconductor devices increases, the required aspect ratio of a contact hole increases significantly. This requires an increase in dry etching selectivity achieved between two different kinds of insulating layers used in a SAC etching process.
In general, a SAC etching process utilizes a combination of a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer as the insulating layers. Specifically, when dry etching a SiO2 layer, a Si3N4 layer can be used as a spacer and etch mask. A commonly obtainable etching selectivity of SiO2 to Si3N4 is only about 5:1, while the SiO2 to Si3N4 dry etching selectivity that is required in an actual process of a stable semiconductor device is about 20:1.
To solve this problem, recent studies focus on obtaining a higher etching selectivity ratio of SiO2 to Si3N4 in a dry etching process itself. For example, representative approaches include a method of increasing the concentration of a CFx radical within plasma used as an etchant by heating the wall of a chamber in which dry etching is performed, and development of a dry etching process that uses C4F8, C5F8 or C3F6 as a new fluorocarbon series gas having a high C/F ratio. Furthermore, an attempt to suppress excessive occurrences of F radicals due to extreme dissociation within plasma with the development of a new plasma source having low electron temperature has been known. However, at the present time, it is known that new dry etching processes still achieve SiO2 to Si3N4 dry etching selectivity of only 10:1
To solve the above problems, it is an objective of the present invention to provide a method of manufacturing a self-aligned contact hole, wherein the process stability required for semiconductor device manufacturing can be provided by lowering the dependence of a self-aligned contact (SAC) etching process on etching selectivity between different kinds of insulating layers used in the SAC etching process.
Accordingly, to achieve the above objective, the present invention provides a method of manufacturing a self-aligned contact hole in a semiconductor device. According to the method, first, a plurality of gate patterns are provided on a semiconductor substrate interposing a gate insulating layer. The gate patterns may be composed of a conductive polycrystalline silicon. Then, a first insulating pattern for filling the gap between the gate patterns and exposing the top surface of the gate patterns is formed. The first insulating pattern may be comprised of silicon oxide. Next, the first insulating pattern is selectively etched by self-aligned contact etching to form a first contact hole for exposing the semiconductor substrate. Next, a spacer is formed along a sidewall of the first contact hole. The spacer may be comprised of silicon nitride. Then, a first plug comprised of a conductive silicon layer, which exposes the top surface of the spacer and fills the first contact hole, is formed. The first plug and the gate pattern are partially etched back to a predetermined thickness from the top surface of the first plug and the gate pattern, using the top surface of the first plug and the gate pattern as an etch mask, so that the top portion of the spacer is projected higher than the surface of the first plug and the gate pattern. Then, a second plug layer comprised of a conductive silicon layer, which exposes at least the gap between the projected spacers, is formed on the first plug and the gate pattern, wherein the thickness of the second plug layer in that portion filling the spacers is greater than that deposited on the gate pattern. Next, the second plug layer is etched back to a uniform thickness along the entire surface to expose the sides of the spacer and the first insulating pattern adjacent to the gate pattern, and then the portion of second plug layer filling the gap between the spacers is separated to form a second plug connected to the first plug. In this case, the etchback is performed by wet etching.
After forming the second plug, a metal silicide layer may be further selectively formed on the top surface of the gate pattern. In this case, the metal silicide layer may be selectively formed on the surface of the second plug as well.
A capping protective pattern, which exposes the top surface of the second plug, fills at least the gap between the first insulating pattern and the spacer, and is connected to the spacer to cover and protect he gate pattern, is formed. A second insulating pattern having a second contact hole which exposes at least the top surface of the second plug is formed on the capping protective pattern.